SYSTEM LEVEL THERMAL PERFORMANCE EVALUATION OF INVERTED EXPOSED PAD PACKAGES

摘要

An extensive 3-D conjugate numerical study is conductedrnto assess the thermal performance of the novel 54 lead SOICrn(with inverted exposed Cu pad) packages for automotivernapplications. The thermal performance of the modifiedrndesigns with exposed pad are investigated, ranging fromrnsmaller die/flag size to larger ones, with single or multiplernheat sources operating under various powering conditions.rnThe thermal performance is compared to other existingrnpackages with typical application to the automotive industry.rnThe impact of the lead frame geometrical structure and diernattach material on the overall thermal behavior is evaluated.rnUnder one steady state (4W) operating scenario, thernpackage reaches a peak temperature of 117.1°C,rncorresponding to a junction-to-heatsink thermal resistance Rjhsrnof 4.27°C/W. For the design with a slightly smaller Curnalloy exposed pad (Cu Alloy), the peak temperature reachedrnby the FETs is 117.8°C, slightly higher than for the designrnwith the intermediate size flag. In this case, the junction-toheatsinkrnthermal resistance Rj-hs is 4.45°C/W. The worstrncase powering scenario is identified, with 1.312W/FET andrntotal power of 10.5W, barely satisfying the overall thermalrnbudget. The variation of the peak (junction) temperature isrnalso evaluated for several powering scenarios.rnFinally, made comparison with a different exposed padrnpackage. The impact of higher thermal conductivity (solder)rndie attach is evaluated and compared to the epoxy die attachrnin the 54 lead SOIC package. Several cases will be evaluatedrnin the paper, with an emphasis on the superior thermalrnperformance of new packages for automotive applications.