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An improved three-state master equation model for capacitively coupled single-electron transistor

机译:电容耦合单电子晶体管的改进三态主方程模型

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In this paper, we develop an improved semi-classical steady-state model for capacitively coupled single-electron transistor (SET). This SET model is based on the three-state steady-state master equation, but has some revision at different device parameters, and is thus called the improved three-state master equation model. We calculate IDS-UDD, IDS-UG, and GDS-UDD characteristics for different device parameters. We also present corresponding characteristics calculated by the Monte Carlo method and the full master equation method in most cases. The results demonstrate that the new approach is comparable to the Monte Carlo method and the full master equation method in precision, even in the high voltage region of VDS, and it simplifies the calculation and improves the speed of numerical simulation. This model can easily be embedded in the SPICE program. Of course, the validity of this embedded model depends on whether the SET can be regarded as a separate component in the circuit.
机译:在本文中,我们为电容耦合单电子晶体管(SET)开发了一种改进的半经典稳态模型。该SET模型基于三态稳态主方程,但是在不同的器件参数上有所修改,因此被称为改进的三态主方程模型。我们计算I DS -U DD ,I DS -U G 和G DS -U DD 特性。在大多数情况下,我们还介绍了通过蒙特卡洛方法和完全主方程方法计算出的相应特征。结果表明,即使在V DS 的高压区域,该新方法在精度上也可与Monte Carlo方法和完全主方程法相媲美,简化了计算并提高了速度。数值模拟。该模型可以轻松地嵌入SPICE程序中。当然,该嵌入式模型的有效性取决于SET是否可被视为电路中的独立组件。

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