IC Yield Prediction and Analysis Using Semi-Empirical Yield Models and Test Data

摘要

This paper presents the results of an extension to the concept of Micro-Yield (or Micro-Event) modeling presented in . We have developed a design attribute extraction and yield prediction software system that ― given the characterization of a semiconductor process via complex test chips that we call Characterization Vehicle test chips (or CV test chips), an IC product layout and a set of proprietary yield models ― computes detailed contributions of different yield models, of geometrical chip regions and of parts of the chip circuitry to the overall chip yield. The organization of the computed output allows easy comparison of predicted yields to inspection and electrical test measurements, where the electrical tests can include failure bit maps (FBM) for memories and scan test results for logic circuits. After we review the concept of the Yield Impact Matrix (YIMP), we define a more general Micro-Event paradigm and introduce the Extended YTMP. We discuss its application to yield loss root-cause analysis, review related work and present example applications of the overall system built around this concepts.