APF~(R) Pitch-Halving for 22nm Logic Cells using Gridded Design Rules

摘要

The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer AP(R)-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela CanvasTM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.