The AES Encryption and Decryption Realization Based on FPGA

摘要

With the development of networking technology, Hardware encryption technology will become an irreplaceable safety technology. In this paper, a method of AES encryption and decryption algorithm implemented on the same FPGA is presented, where a 128-bit key size mode is implemented, Modelsim simulation test results are demonstrated, the correctness of logic function of the system is verified, and system resource occupancy is presented and briefly analyzed to verify the reliability of the method. Practice proving it is an optimized hardware encryption and decryption method.