SINGLE-EVENT EFFECTS CHARACTERIZATION AND SOFT ERROR MITIGATION IN 90nm COMMERCIAL-DENSITY SRAMs

摘要

SRAM reliability faces serious challenges due to radiation-induced soft errors in aggressively scaled CMOS technologies. The increasing frequency of single-bit upsets and more recently multi-bit upsets (MBU) limits the efficacy of conventionally used single-bit error correcting codes (ECC). Additionally, techniques used in achieving dense packing of SRAM cells may potentially increase the single-event latchup sensitivity of these technologies. To characterize these single-event effects (SEE) for SRAMs in sub-100nm technologies, two prototype SRAM ICs have been designed in two characteristic 90nm bulk-CMOS commercial processes. To evaluate the effectiveness of soft error mitigation techniques, especially in the presence of MBU, two different ECC schemes with increasing error correction capability were implemented. SEE irradiation tests performed on these SRAMs reveal that MBUs are the dominating contributor to overall soft error rate, and their range could be as large as 13-bits. These test results validate the effectiveness of a mathematical model that shows how an effective bit error rate of 10~(-10) errors/bit-day can be achieved. Tests also show improved resilience of these technologies against single-event latchup, provided supply voltages are 1.1V or below.