CMP-less Planarization Technology with SOG/LTO Etchback for Low Cost 70nm Gate-Last Process

摘要

A novel 70nm gate-last process featuring with CMP-less spin-on glass/low-temperature oxide (SOG/LTO) etchback method for developing high performance low cost logic platform is demonstrated. The special 3-step sacrificial etchback process all in one RIE chamber is developed to realize the pseudo global planarization on the composite SOG/LTO 2-layer structure. The finally fabricated PMOSFETs demonstrate nice electrical characteristics as well as similar uniformity distribution to that of planarization process.