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DARTS: a low-cost high-performance FPGA implemented real-time control platform for adaptive optics

机译:DARTS:低成本,高性能,FPGA实现的自适应光学实时控制平台

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Durham University's Centre for Advanced Instrumentation (CfAI) are currently producing a generic high-performance low-cost real-time control system (RTCS) for adaptive optics (AO) based on Field Programmable Gate Array (FPGA) technology. This platform, labelled DARTS, 'Durham Adaptive optics Real Time System', will primarily be used as the controller for Durham's enhanced Rayleigh Technical Demonstrator (RTD) system. However, DARTS could be used as a low latency control system for existing AO instruments or could be used for future 'budget' AO Natural Guide Star (NGS) and/or Laser Guide Star (LGS) RTCS. DARTS uses an FPGA device to host an end-to-end modular real-time AO pipeline connected to a Wishbone control bus. The FPGA takes advantage of the pipeline's highly parallel computationally intensive tasks which usually are calculated in series by a system processor. DARTS hopes to increase the obtainable control loop frequency and reduce the computational latency of the RTD's RTCS. DARTS is capable of high bandwidth I/O due to the implementation of the serial Front Panel Data Port (sFPDP) industrial protocol. The hardware's I/O design is modular, allowing for the future connection of various WFSs and DMs via signal converters. Various communications architectures are suggested to allow non real-time configuration and visualisation data to flow between the wishbone control bus and a processing device, either externally or internally to the FPGA device.
机译:达勒姆大学高级仪器中心(CfAI)目前正在基于现场可编程门阵列(FPGA)技术生产用于自适应光学(AO)的通用高性能低成本实时控制系统(RTCS)。该平台被标记为DARTS,称为“ Durham自适应光学实时系统”,将主要用作Durham增强型Rayleigh技术演示器(RTD)系统的控制器。但是,DARTS可以用作现有AO仪器的低延迟控制系统,也可以用于未来的“预算” AO自然导星(NGS)和/或激光导星(LGS)RTCS。 DARTS使用FPGA器件来托管连接到Wishbone控制总线的端到端模块化实时AO管道。 FPGA利用了流水线的高度并行计算密集型任务,这些任务通常由系统处理器串行计算。 DARTS希望增加可获得的控制环路频率并减少RTD RTCS的计算延迟。由于串行前面板数据端口(sFPDP)工业协议的实现,DARTS能够进行高带宽I / O。硬件的I / O设计是模块化的,允许将来通过信号转换器连接各种WFS和DM。建议使用各种通信体系结构,以允许非实时配置和可视化数据在叉骨控制总线和处理设备之间(在FPGA设备的外部或内部)流动。

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