A hardware efficient technique for linear convolution of finite length sequences

摘要

point HOT is based on a K-point DFT. However, due to the complexity of the HOT convolution, it was not easily realizable on hardware. This paper first modifies the HOT based convolution technique to make it more suitable for hardware realization. Then, FFT based convolution and the proposed convolution are realized by using similar architectures. To evaluate the effectiveness of the implementation, we compare the proposed convolution with the FFT convolution for a length of 256. The Mean Square Error (MSE), space requirements, and maximum throughput are used in the analysis of the implementations. Field Programmable Gate Arrays (FPGAs) are used to implement the algorithms. We have shown almost 45% reduction in space compared to FFT convolution while maintaining similar MSE and slightly worse throughput.