Physical origins of slow traps for ALD high-k dielectrics on GeOx/Ge interfaces

摘要

Ge with higher electron and hole mobility is an attracting channel material for next generation MOSFETs[1].While Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge structures fabricated by PPO (plasma post oxidation) have been reported asone of the realistic gate stacks with very thin EOT [2-3], a large amount of slow traps existing at the Ge MOS interfaces andresulting inferior reliability have been one of the most critical remaining issues for Ge CMOS realization [4-6]. We haverecently found that the slow traps for electrons could exist inside GeOx formed by PPO [7]. However, the physical origin of theslow trap generation for electrons and holes has not been understood yet. In this study, we systematically compare the slow trapdensity of electron and holes for the Al2O3/GeOx/Ge interfaces with different GeOx thickness prepared by post or pre plasmaoxidation for ALD Al2O3/Ge stacks. Also, we examine the influence of high-k post deposition on Nst in the high-k/GeOx/GeMOS interfaces to study the physical origin of slow traps.