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Reducing False Aborts in STM Systems

机译:减少STM系统中的错误中止

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Transactional memory (TM) continues to be the most promising approach replacing locks in concurrent programming, but TM systems based on software (STM) still lack the desired performance when compared to fine-grained lock implementations. It is known that the critical operation in TM systems is to ensure the atomicity and isolation of concurrently executing threads. This task is known as the read/write-set validation. In attempt to make this process as fast as possible, STM systems usually use ownership tables to perform conflict detection, but this approach generates false positive occurrences, which result in false aborts. This paper shows the real impact of false aborts and how its relevance increases along with the number of concurrent threads, showing it is an essential factor for TM systems. We propose two different techniques to avoid false aborts, showing its benefits and limitations. The first is a collision list attached to the existing hash table. The second is a full associative memory mapping between the addresses and its version information. We achieved significant performance improvements in some STAMP benchmark programs, resulting in speedups up to 1.5x. We also show that speedups become higher when the number of parallel threads increases.
机译:事务性内存(TM)仍然是取代并发编程中的锁的最有希望的方法,但是与细粒度的锁实现相比,基于软件(STM)的TM系统仍然缺乏所需的性能。众所周知,TM系统中的关键操作是确保并发执行线程的原子性和隔离性。此任务称为读取/写入集验证。为了尽可能快地完成此过程,STM系统通常使用所有权表执行冲突检测,但是这种方法会产生误报,从而导致错误中止。本文展示了错误中止的真正影响以及错误相关性如何随并发线程数的增加而增加,这表明它是TM系统的重要因素。我们提出了两种不同的技术来避免错误中止,以显示其好处和局限性。第一个是附加到现有哈希表的冲突列表。第二个是地址及其版本信息之间的完整关联内存映射。我们在一些STAMP基准测试程序中实现了显着的性能改进,从而使速度提高了1.5倍。我们还表明,当并行线程数增加时,加速会变得更高。

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