Research and Implementation of a Reconfigurable Parallel Low Power E0 Algorithm

摘要

A low power and dynamic reconfigurable parallel hardware architecture of E0 algorithm is presented, which can satisfy sixteen different LFSRs in the Bluetooth telecommunication systems. Moreover, the paper proposes the parallel realization of LFSR, which can support to generate N parallel sequence in each step. The new LFSR design techniques can be also useful in any LFSR. To reduce the conventional switching activity, we proposed the clock-gating technique to implement the LFSR. As to the different low power method, the paper performs detailed comparison and analysis. The design has been realized using Altera's FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18μm CMOS process, the result proves Up to 40% power consumption was reduced compared with conventional EO implementation. And the critical throughput rate can achieve 166Mbps.