Adding a New Dimension to Physical Design

摘要

Three-dimensional (3D) technologies have the potential to provide major benefits to integratedrncircuit design. An advanced 3D chip consists of multiple tiers of two-dimensional (2D) circuitry,rnstacked vertically over each other, with very small intertier distances. Such technologies offerrnnumerous benefits over conventional 2D designs. First, by stacking multiple 2D tiers, it is possiblernto increase the number of transistors within a package: in other words, 3D offers increasedrnintegration using an approach that is orthogonal to device scaling. Second, the small intertierrndistances imply that the histogram of wire length distributions is significantly altered, enablingrncritical wires to be made very short. Third, 3D offers opportunities for integrating heterogeneousrntechnologies into a single chip, enabling much more versatility in the types of chips we can build.rnFundamentally, the shift from 2D to 3D is topological, and holds numerous physical designrnchallenges. In addition, several effects that were critical in 2D are further accentuated in 3D. Forrnexample, the increased current required by a 3D stack, as compared to a 2D chip with the samernfootprint, brings forth twin problems: how do we get the current in (i.e., perform reliable powerrndelivery), and how do we get the heat out (i.e., perform thermal management)? Solutions tornproblems such as these can come from the architectural level and go down to much finerrngranularities. This talk overviews prior work in the area, and surveys the challenges andrnopportunities ahead.