A GA-based Static Test Compaction Algorithm for Sequential Circuits

摘要

This paper applies genetic algorithm (GA) in test compaction for sequential circuits. The algorithm compacts test set generated by ATPG (Automatic Test Pattern Generation) tool under the assumption that the test set can be partitioned into some sub-sequences, each containing redundant vectors that can not detect faults or perform state transition. The proposed algorithm removes these redundant vectors from the test set. Experimental results show that the GA-based algorithm can effectively reduce the size of test sets with acceptable computational cost and maintain the fault coverage of the original test set.