Failure Mode Verification and Mechanism Analysis for ASIC Output Driver

摘要

The applications of custom-built monolithic integrated circuit (ASIC) have established an important method, for realizing miniaturization application system. But its reliability have also become one of the focused problems which customer has paid special attention to. This paper taking the CMOS monolithic integrated circuit of an ASIC output driver designed for a certain model system as an example, has performed a deep failure analysis of the ASIC output driver based on the summarization of the failure data in the engineering applications in recent years. The verification method and acting mechanism of gate-breakdown failure mode has been described in this paper. Some problems such so that the maximum breakdown voltage between drain and source of output driver can not satisfy the requirement of end-user design data and so on have also been pointed out. We consider the thinner of gate oxide layer, and the less surplus of withstand voltage between gate and drain are the direct causes of gate-breakdown failure. Some technology methods for increasing breakdown voltage between drain and source and overcoming gate-breakdown failure problem from improving fabricating process and artwork design, have been presented.