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Innovations in Fault Isolation Methods for 3D Packages with 10X Improvement in Accuracy

机译:3D封装的故障隔离方法创新,精度提高10倍

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3D package technology has become a product differentiator to be competitive in the market place by delivering better performance with smaller footprint at a cost-effective way. It integrates multiple functional components into one device thus reducing development effort of product manufacturers and enabling faster time-to-market. As more components are stacked together and planar features decrease at the same time, 3D package technology brings many new challenges for electrical fault isolation and failure analysis. First of all, since the stacked components are often owned by different suppliers, it is critical to be able to non-destructively isolate the failure to the defective component so that issues can be addressed by the component owners. Secondly, defect localization accuracy has become increasingly challenging because the defect is now deeply buried inside the package, and it becomes more difficult for the conventional fault isolation tools to "see" them. Adding to these technical challenges are the ever demanding volume and through-put time requirements. These challenges require more capable fault isolation tools and techniques with better accuracy, resolution and sensitivity. Lock-in thermography (LIT) is a powerful, non-contact and non-destructive technique that has been successfully applied for electrical fault isolation of 2D packages. Yet its success in 3D packages has been limited because of its accuracy, extensive data collection and in-consistent results as reported by many cases, studies and our own use experience. This paper discusses the challenges LIT faces with respect to its application to 3D packages, examines the key elements that affect its effectiveness from a fundamental way, and presents some new developments that improves its accuracy and efficiency as demonstrated by successful case studies.
机译:3D封装技术通过以经济高效的方式提供更好的性能和更小的占位空间,已成为在市场上具有竞争力的产品差异化产品。它将多个功能组件集成到一个设备中,从而减少了产品制造商的开发工作,并加快了产品上市时间。随着更多的组件堆叠在一起,同时平面特征减少,3D封装技术为电气故障隔离和故障分析带来了许多新挑战。首先,由于堆叠的组件通常由不同的供应商拥有,因此至关重要的是,能够以非破坏性方式隔离故障组件的故障,以便组件所有者可以解决问题。其次,缺陷定位的准确性变得越来越具有挑战性,因为缺陷现在已经深深地埋在封装内部,而传统的故障隔离工具很难“看到”它们。这些技术挑战之外,还有不断增长的数量和吞吐量要求。这些挑战要求功能更强大的故障隔离工具和技术具有更高的准确性,分辨率和灵敏度。锁定热成像(LIT)是一项功能强大,无接触且无损的技术,已成功应用于2D封装的电气故障隔离。然而,由于其准确性,广泛的数据收集以及许多案例,研究和我们自己的使用经验所报告的不一致结果,其在3D封装中的成功受到了限制。本文讨论了LIT在将其应用于3D软件包方面所面临的挑战,从根本上考察了影响其有效性的关键因素,并提出了一些新的进展,这些改进提高了准确性和效率,如成功的案例研究所示。

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