HARDWARE DESIGN OF A HIGH-PRECISION AND FAULT-TOLERANT CLOCK SUBSYSTEM FOR CAN NETWORKS

摘要

One reported weakness of the Controller Area Network protocol is its lack of a clock synchronization service. In this paper, we present the architecture of a hardware clock subsystem which provides CAN networks with such a clock synchronization service. Our architecture presents significant advantages in front of previously suggested solutions. First, it is orthogonal to any CAN network. Second, it is compatible with timer-driven as well as clock-driven real-time distributed systems. Third, it achieves high-precision clock synchronization. And fourth, it presents a fault-tolerant behaviour.