首页> 外文会议>2019 56th ACM/IEEE Design Automation Conference >ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications
【24h】

ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications

机译:ShuntFlow:用于流媒体应用程序的高效且可扩展的数据流加速器体系结构

获取原文
获取原文并翻译 | 示例

摘要

Streaming processing is an important and growing class of applications for analyzing continuous streams of real time data. Slidingwindow aggregations (SWAGs) dominate the computation time in such applications and dictate an unprecedented computation capacity which poses a great challenge to the computing architectures. General-purpose processors cannot efficiently handle SWAGs because of the specific computation patterns. This paper proposes an efficient accelerator architecture for ubiquitous SWAGs, called ShuntFlow. ShuntFlow is a typical type of Kernel Processing Unit (KPU) where “Kernel” represent two main categories of SWAG operations widely used in streaming processing. Meanwhile, we propose a shunt rule to enable ShuntFlow to efficiently handle SWAGs with arbitrary parameters. As a case study, we implemented ShuntFlow on an Altera Arria 10 AX115N FPGA board at 150 MHz and compared it to previous approaches. The experimental results show that ShuntFlow provides a tremendous throughput and latency advantage over CPU and GPU implementations on both reduce-like and index-like SWAGs.
机译:流处理是用于分析连续的实时数据流的重要且正在增长的一类应用程序。滑动窗口聚合(SWAG)支配了此类应用程序的计算时间,并规定了空前的计算能力,这给计算架构带来了巨大挑战。由于特定的计算模式,通用处理器无法有效处理SWAG。本文提出了一种适用于普遍存在的SWAG的高效加速器架构,称为ShuntFlow。 ShuntFlow是一种典型的内核处理单元(KPU),其中“内核”代表在流处理中广泛使用的SWAG操作的两个主要类别。同时,我们提出了一种分流规则,以使ShuntFlow能够有效处理具有任意参数的SWAG。作为案例研究,我们在150 MHz的Altera Arria 10 AX115N FPGA板上实现了ShuntFlow,并将其与以前的方法进行了比较。实验结果表明,在类似缩减和类似索引的SWAG上,与基于CPU和GPU的实现相比,ShuntFlow具有巨大的吞吐量和延迟优势。

著录项

  • 来源
  • 会议地点 Las Vegas(US)
  • 作者单位

    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences, YUSUR Technology Co., Ltd.;

    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences, YUSUR Technology Co., Ltd.;

    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences, YUSUR Technology Co., Ltd.;

    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences, YUSUR Technology Co., Ltd.;

    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences, YUSUR Technology Co., Ltd.;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Microsoft Windows; Kernel; Accelerator architectures; Field programmable gate arrays; Computational efficiency; Real-time systems;

    机译:Microsoft Windows;内核;加速器体系结构;现场可编程门阵列;计算效率;实时系统;;

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号