Estimation of maximum power and instantaneous current using agenetic algorithm

摘要

We present a genetic-algorithm-based approach for estimating thenmaximum power dissipation and instantaneous current through supply linesnfor CMOS circuits. Our approach can handle large combinational andnsequential circuits with arbitrary but known delays. To obtain accuratenresults we extract the timing and current information fromntransistor-level and general-delay gate-level simulation. Ournexperimental results show that the patterns generated by our approachnproduce on the average a lower bound on the maximum power which is 41%ntighter than the one obtained by weighted random patterns for estimatingnthe maximum power. Also, our lower bound for the maximum instantaneousncurrent is 21% tighter as compared to the weighted random patterns