A full function Verilog(R) PLL logic model

摘要

This paper describes the full function model of a phase-lockednloop (PLL) in a logic simulator. In contrast to conventional models thatnbypass the PLL function, this Verilog model accurately represents allnmajor characteristics of a PLL. It allows the simulation of the effectnof the actual filter elements. It can accurately model clock deskew of anclock tree as well as synthesize other frequencies from the input clock.nIt produces a clock detect signal after a realistic lock sequence. Thenuser has the option to add jitter to the PLL output. The model performsnthree orders of magnitude faster than an equivalent circuit model