A clock methodology for high-performance microprocessors

摘要

This paper discusses an effective clock methodology for the designnof a high-performance microprocessor. Key attributes include thenclustering and balancing of clock loads, multiple clock domains, anbalanced clock router with variable width wires to minimize skew,nhierarchical clock wiring, automated verification, an interface to thenCadence Design Framework II^TM environment, and a completennetwork model of the clock distribution, including loads. This clocknmethodology enabled creation of the entire clock network, includingnverification, in less than three days with approximately 180 ps of skew