A hierarchical decomposition methodology for single-stage clockcircuits

摘要

This paper describes a methodology for designing the interconnectndistribution for single-stage clock circuits using a hierarchicalndecomposition. This new method of splitting the design into global andnlocal distributions improves the optimization efficiency and enhancesnboth wireability and performance. A novel use of the Delaunayntriangulation provides a means for efficiently constructing andnoptimizing the local distribution. The combination of these global andnlocal solutions produces layouts with less wirelength and an averagen3× performance improvement over flat solutions while keeping thenworst case skew below 50 ps. When these designs are wiresized, theynachieve a 25% reduction in wire area over their flat circuitncounterparts due to the reduction in downstream capacitive wire loading