Low Power Column ADC for CMOS Imagers

摘要

Since most CMOS imagers read out large pixel sets (e.g. lines) at the same time, we can choose a level of parallelism to do analog to digital conversion (ADC). This paper presents the design, simulation and measurement results of a 10 bit fully parallel ADC in a 0.35 μ, process, taking 1 mm~2 and 7 mW to convert 50 VGA images per second.