首页> 外文会议>26th European Solid-State Circuits Conference, Sep 19-21, 2000, Stockholm, Sweden >A High-Efficiency Back-Bias Generator with Cross-Coupled Hybrid Pumping Circuit for sub-1.5 V DRAM applications
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A High-Efficiency Back-Bias Generator with Cross-Coupled Hybrid Pumping Circuit for sub-1.5 V DRAM applications

机译:具有交叉耦合混合泵浦电路的高效反向偏置发生器,适用于低于1.5 V的DRAM应用

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摘要

Based on the study about the previously developed back-bias generators, a new high-efficiency back-bias generator with the Cross-coupled Hybrid Pumping Circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous ones, throwing away the disadvantages. CHPC2 shows ∣V_(BB)∣/V_(CC) as large as 98% even at low V_(CC)=0.9 V, strongly addressing that it will be suitable at low voltage DRAM applications. Moreover, CHPC2 exhibits much better pumping efficiency and larger pumping current over the previous ones with wide R_L range at V_(CC)=1.2 V.
机译:在对以前开发的反向偏置发生器进行研究的基础上,本文提出了一种具有交叉耦合混合泵浦电路2(CHPC2)的新型高效反向偏置发生器。 CHPC2仅利用了以前的优点,而摒弃了这些缺点。 CHPC2即使在低V_(CC)= 0.9 V时也显示高达98%的∣V_(BB)∣ / V_(CC),有力地解决了这一问题,它将适用于低压DRAM应用。此外,CHPC2在V_(CC)= 1.2 V时具有较宽的R_L范围的情况下,具有比以前更高的泵浦效率和更大的泵浦电流。

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