An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

摘要

An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.