3-D ICs: Motivation, Performance Analysis, and Technology

摘要

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor industry roadmap predicts, that beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects. This analysis is based on dividing a chip into separate blocks, each occupying a physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Various technologies being investigated for 3-D fabrication are reviewed. Finally, implications of 3-D architecture on several circuit designs are also discussed.