Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal?

摘要

To carry out fast but accurate tsunami simulation after a major earthquake, we have developed an FPGA-based custom computing machine for high-speed but low-power tsunami simulator. We design a stream processing element (SPE) which is hardware based on pipelining and data-flow for tsunami computation. This paper presents design-space exploration for spatial and temporal parallelism of SPEs.