Effect of chip size on thermal fatigue of flip-chip bump

摘要

Due to miniaturization and high density of integrated circuits, bump solders are widely used in electronic industry for assembling electronic components on the connection of chip to substrate. Under the various operation conditions, solder bumps are subjected to cyclic stress and failed by thermal fatigue. To ensure the reliability of electronic products, it is becoming important to predict the fatigue failure of the solder bumps. In this study, effects of chip size on thermal fatigue life of the solder bumps were investigated by experiments and elastic-plastic finite element analysis, comparing four sizes of flip-chip devices to summarize the effect of chip sizes on temperature and stress/strain distribution, it turns out that strain/stress of corner bump was increasing with the chip size, at the end, we proposed a method to enhance the thermal fatigue life of solder bumps by using Parylene to protect the solder bump, results showed that Parylene layer could improve the strain and stress distribution significantly.