School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA;
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA;
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA;
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA;
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA;
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85281, USA;
Neurons; Sensors; Computer architecture; Degradation; System-on-chip; Random access memory; Switches;
机译:基于尖峰神经网络的LEGION图像分割,使用紧凑型可扩展神经形态架构上实现的标准化突触权重
机译:基于军团的图像分割,通过使用正规化的突触重量在紧凑的可伸缩神经形状架构上实现的标准化突触重量
机译:大规模卷积神经网络的双层并行训练架构
机译:XNOR-RRAM:二元神经网络的可扩展和平行电阻突触架构
机译:并行硬件体系结构的使用对仿真神经网络训练过程的影响。
机译:基于Memristor的二元卷积神经网络架构可配置神经元
机译:NAND闪存的新型突触架构,用于高稳健和高密度量化的神经网络,其中二进制神经元激活(1,0)
机译:神经网络性质和局限性的计算分析:走向新的学习平行架构