A fault avoidance approach with test set generation in combinational circuits using genetic algorithm

摘要

In this paper a stuck-at-fault avoidance approach in combinational VLSI circuits using genetic algorithm (GA) by comparing two complementary circuits has been proposed. Analysis of whole test set generation for a fault model helps to reduce the fault detection probability in combinational circuits. The GA proves to be a very helpful algorithm in finding the highest suitable number of test patterns in reference to most suitable solution for any problem. The paper focuses on detectability concept which is a way to find out the fault present in the circuit. Undetectability is a way to avoid the detected fault which is present in the circuit. In this paper we are taking the complementary circuit of reference fault model and analyzing the results for both circuits by generating test sets. In this paper results are obtained for single stuck-at-fault in the ISIS PROTEUS (C12) benchmark circuit. Experimental results showed that the genetic algorithm is helpful in findings the best method to avoid fault in terms of fault coverage and fitness factor.