Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

摘要

This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M>N test vectors, without loss of fault coverage. During test generation, we also find a lower bound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.