Minimal-area loop pipelining for high-level synthesis with CCC

摘要

Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain HDL codes from highlevel language functional descriptions. With high-level synthesis it becomes easier to design coprocessors, accelerators, and other special-purpose hardware. Nonetheless, compiler optimizations can improve efficiency of automatically generated hardware descriptions and make high-level synthesis to become the dominant technology to build more complicated hardware as well. Compilers, well known and explored software tools, can allow programmers to use their software skills on hardware programming, without any language compromises. Furthermore, compiler optimizations transform the input code, in order to produce a high-quality high-performance output hardware description. In this paper, we discuss compiler issues for high-level synthesis, and in particular, the incorporation of loop pipelining in the C language front end of the CCC high-level synthesis tool. We also present a novel pipelining technique that minimizes the area used for the pipeline prologue and epilogue. Results from experiments on the Livermore loops and Mpeg2 open-source codes validate our technique.