Minimum area layout of high bandwidth folded cascode operational amplifier using SCL 180nm CMOS technology

摘要

This paper presents the design and layout of a high speed folded cascode operational amplifier with the minimum layout area in SCL 180nm CMOS technology. The analog circuits are more vulnerable to parasitic due to its inherently large W/L. In order to accomplish the desired performance, parasitic issues must be clearly handled. The layout of the Opamp is done with the standard method; larger parasitic are generated in this layout, thus poor performance. To tackle the performance degradation due to parasitic, layout techniques such as multi-finger and common centroid layout are used which drastically improve the performance.