Department of Telecommunication, R.V. College of Engineering, Bengaluru, India;
Department of Telecommunication, R.V. College of Engineering, Bengaluru, India;
Department of Telecommunication, R.V. College of Engineering, Bengaluru, India;
Department of Telecommunication, R.V. College of Engineering, Bengaluru, India;
Adders; Adiabatic; Computer architecture; Power dissipation; Logic gates; Delays; Transistors;
机译:利用静态CMOS逻辑和绝热逻辑的低功耗8位超前进位加法器的设计与实现
机译:基于绝热逻辑的低功耗进位选择加法器的设计
机译:基于绝热逻辑的低功耗进位选择加法器的设计
机译:低功耗8位携带选择加法器使用绝热逻辑
机译:超低功耗,单时钟功率绝热电路逻辑。
机译:切片选择可调翻转绝热低峰值功率激励(STABLE)脉冲
机译:利用静态CMOS逻辑和绝热逻辑的低功耗8位超前进位加法器的设计与实现