Single bit hybrid full adder cell by gate diffusion input and pass transistor logic technique

摘要

In this paper, single bit full adder hybrid circuit has been proposed which consist of two techniques i.e. Pass transistor Logic (PTL) and Gate Diffusion Technique (GDI). Several logic families are described by PTL which is utilized in the architecture of integrated circuits. PTL technique is used to decreases the number of transistors in the circuits to make different gates of logic by eradicating redundant transistors. GDI technique is utilized for the low power consumption. In this paper CADENCE VIRTUOSO tool is being used and all the simulation work is done on it by utilizing the technology node at 180nm along with a supply voltage of 1.8V. The simulation result represents that the proposed architecture of single bit hybrid full adder cell absorbs 53% less power in comparison with hybrid full adder [5], 5% less power in comparison with 3T XNOR [6], 58% less power in comparison with 8T full adder cell [6] and 86% less power in comparison with Adder using MDCVSL [8]. As we know that power and propagation delay both are varying inversely but still the propagation delay is not affected much and it is almost similar than the existing designs.