A highly linear 5GS/s voltage-to-time converter for time-based analog-to-digital converters

摘要

In this paper, a new Voltage-to-Time Converter design is presented. The proposed scheme is based on a new current starved inverter with its analog input adopting a folding structure. Better linearity is achieved for the new scheme. Proposed VTC can accept +/-0.5V at 5GS/s sampling rate with a linearity maximum error of 2.5%. The simulation results show that an ENOB of 7.5 bits is achieved with an output range of +/-51ps in 65nm CMOS process.