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A high linear voltage-to-time converter (VTC) with 1.2 V input range for time-domain analog-to-digital converters

机译:具有1.2 V输入范围的高线性电压与时转换器(VTC),用于时域模数转换器

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摘要

This paper presents a high linear voltage-to-time converter (VTC) with wide input range of over 1.2 Vp-p, (diff) for the high-speed high-linear time-domain (TD) analog-to-digital converters (ADC). Different from the conventional VTC, the proposed VTC samples the input as the initial charge voltage, and apply current source independent of the input for charge process. Thanks to the high-linear sample and hold (S/H) circuit and low-mismatch current source, the input range and linearity of the proposed VTC are greatly improved. Also, a low propagation-delay comparator is designed for high-speed VTC. The VTC is fabricated in 65 nm CMOS process, occupying an area of 0.012 mm(2), consuming power of 0.48 mW. The measured results show that conversion gain of the VTC is as high as 1.95 ns/V. DNL/INL is suppressed within -0.32-0.38 LSB and -0.5-0.6 LSB, respectively. In 250 MHz full Nyquist frequency, SFDR is measured over 66 dB.
机译:本文介绍了高输入范围内的高线性电压与时转换器(VTC),用于高速高线性时域(TD)模数转换器( ADC)。与传统的VTC不同,所提出的VTC将输入作为初始电荷电压进行采样,并涂布与充电过程的输入无关的电流源。由于高线性样品和保持(S / H)电路和低错位电流源,所提出的VTC的输入范围和线性度大大提高。而且,低传播延迟比较器专为高速VTC而设计。 VTC在65nm CMOS工艺中制造,占地0.012毫米(2),消耗功率为0.48 mW。测量结果表明,VTC的转换增益高达1.95 ns / v。 DNL / INL分别在-0.32-0.38 LSB和-0.5-0.6 LSB内抑制。在250 MHz完全奈奎斯特频率,SFDR以超过66 dB测量。

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