Device Simulation Lab, Dept. of Electronics Instrumentation Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;
Device Simulation Lab, Dept. of Electronics Instrumentation Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;
Device Simulation Lab, Dept. of Electronics Instrumentation Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;
Dept. of Electronics Communication Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;
Logic gates; Tunneling; Electric potential; TFETs; Silicon; Analytical models; Boundary conditions;
机译:双金属栅极双栅极隧道FET的分析表面电势和漏极电流模型
机译:双栅异质结构隧道FET漏极电流的物理和解析模型
机译:使用载流子浓度法的双栅隧穿场效应晶体管(DG-TFET)的分析模型
机译:双门隧道FET的隧道基于分析漏极电流模型(DG-TFET)
机译:结合虚拟栅极和转移电子效应的影响,对AlGaN / GaN HFET的漏极电流特性进行分析建模。
机译:具有InAs / Si异质结和源极口袋结构的双栅隧道FET的漏极电流模型
机译:带有INAS / SI异质结和源口袋架构的双栅极隧道FET的排水电流模型