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Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET)

机译:基于隧道路径的双栅极隧道FET(DG-TFET)的分析漏极电流模型

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摘要

This paper presents a 2D analytical model for symmetric double gate Tunnel Field Effect transistor (DG-TFET) based on tunneling path in the channel. The potential profile is obtained by solving 2D Poisson's equation in the rectangular coordinate system. The drain current is extracted by integrating the band to band tunneling generation rate, initial and final tunneling length. The primary focus is on initial tunneling length as it directly influence the drain current amplitude of the device. The DG-TFET shows ON-current improvement as compared with SG-TFET. The validation of analytical results with simulated results is done by TCAD device simulator.
机译:本文提出了一种基于沟道中的隧穿路径的对称双栅隧穿场效应晶体管(DG-TFET)的二维分析模型。通过在直角坐标系中求解二维泊松方程获得电势轮廓。通过积分带间隧穿产生速率,初始和最终隧穿长度来提取漏极电流。主要关注初始隧穿长度,因为它直接影响器件的漏极电流幅度。与SG-TFET相比,DG-TFET的导通电流有所改善。用TCAD设备模拟器完成分析结果与模拟结果的验证。

著录项

  • 来源
  • 会议地点 Sultanpur(IN)
  • 作者单位

    Device Simulation Lab, Dept. of Electronics Instrumentation Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;

    Device Simulation Lab, Dept. of Electronics Instrumentation Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;

    Device Simulation Lab, Dept. of Electronics Instrumentation Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;

    Dept. of Electronics Communication Engg., Institute of Technical Education Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar-751030, India;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Logic gates; Tunneling; Electric potential; TFETs; Silicon; Analytical models; Boundary conditions;

    机译:逻辑门;隧道;电势; TFET;硅;分析模型;边界条件;
  • 入库时间 2022-08-26 13:59:46

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