FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor

摘要

This paper presents the design, implementation and integration of a reconfigurable Intellectual Property (IP)-based co-processor for the COFFEE RISC processor on a Field Programmable Gate Array (FPGA) device. The co-processor is capable of communicating with peripheral devices through the Controller Area Network (CAN) protocol. Although the main target of the co-processor is standard CAN frames, it is able to reconfigure itself in run-time to receive and decode the extended CAN frames. One of the main advantages of the co-processor is full compatibility with the COFFEE processor's requirements. Furthermore, the data transmission between the core and co-processor introduces no workload on the main data bus. In this implementation, the co-processor could achieve the maximum operating frequencies of 493MHz up to 825MHz in slow and fast timing models, respectively. As a result, the implemented co-processor gains (at least) 2.8x speed-up in comparison with the COFFEE processor by consuming a trivial dynamic energy. The ultimate achievement of this work is the new horizon expanded to the COFFEE processor to communicate with CAN-based peripheral devices which makes the core more versatile even for industrial purposes.