A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines

摘要

This paper presents a significant technique to use wide-pulsed-latches to increase the time-borrowing capability and tolerance of variations in near/sub-threshold (Vt) pipelines. Specifically, we use multi-Vt cells to pad the short paths to extend the pulse width up to one third of cycle time while causing minimal overhead in area and power. Moreover, a simpler pulse/clock distribution network design for pulsed-latch based pipelines is proposed. Compared with traditional pulsed-latch based circuits, our technique achieves over 3X higher time to borrow while decreases the complexity of the clock network effectively. The technique is applied to the design of a 0.35V FIR Alter in a 65nm, which achieves 45.2% and 11% improvements in performance and energy efficiency than the flip-flop based implementation, respectively. The measurement results also confirm the robustness of our proposed technique across process, voltage, and temperature variations.