首页> 外文会议>2016 IEEE Asian Solid-State Circuits Conference >A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication
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A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication

机译:一个14.4Gb / s / pin 230fJ / b / pin / mm多层RF互连,用于全球片上网络通信

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A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.
机译:演示了同时进行且可重新配置的多层RF互连(MRI),用于全球片上网络(NoC)通信。建议的MRI接口由基带(BB)和RF波段收发器组成。 BB收发器使用多级信令(MLS)来增强通信带宽。 RF波段收发器利用幅度移位键控(ASK)调制来支持在共享的单端片上全局互连上同时进行通信。还设计了一个锁相环(PLL)以支持完全同步的NoC架构。基于MLS的BB和基于ASK的RF频段分别承载10Gb / s / pin和4.4Gb / s / pin。拟议的系统采用65nm CMOS工艺制造,能量/ b / pin / mm为230fJ / b / pin / mm。

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