首页> 外文会议>2016 IEEE 37th International Electronics Manufacturing Technology amp; 18th Electronics Materials and Packaging Conference >Crack die elimination by comprehensive optimization throughout all assembly process steps
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Crack die elimination by comprehensive optimization throughout all assembly process steps

机译:通过在所有组装过程步骤中进行全面优化来消除裂纹模具

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Over years, the crack die defect was proven cannot be screened effectively through Final Test, therefore it has high risk reaching the end applications. This issue can affect many devices, including some miniature devices such as Small Outline Transistors, SOTXXX Eutectic. In order to eliminate the die crack defect, entire assembly process required optimization; including Saw, Die Attach, Wire Bond, Mold, Plating, Trim/Form and Final Test. Each process step has its own risks and therefore full analysis was conducted on all the possible opportunities. At wafer sawing process, several sawing methods were evaluated, including single cut, step cut, 3 channels cutting, cutting directions and selection of various blade types. With the optimum sawing process, die chipping was minimized to lowest level (only few microns), that resulting to minimum die cracking risk. With that performance, further risk investigation was carried on to understand the stress amount inside the package. There were 2 significant stress factors, die location on flag and trim/form impact to the leads. In order to minimize the effect of the stress, die was attached to the location with the least amount of stress. As for trim/form, this involved new design leadframe fabricated and experimented in production. The leadframe design optimization was completed after compliance to the reasonable stress level, as calculated in the trim/form stress analysis. When new leadframe was subjected to actual trim/form process, actual performance was verified by reliability testing. With the optimum assembly configurations, further safety action was depended to the Final Test capability. There were 2 additional test parameters added to increase effectiveness of screening potential die crack rejects. With the total compilation of all the optimum assembly and test configurations, actual performance monitoring showed total elimination of die crack occurrence. This project becomes good benchmark of any die crack reduction or elimination project.
机译:多年来,已证明裂纹模具的缺陷无法通过最终测试有效地进行筛选,因此在最终应用中具有很高的风险。此问题可能会影响许多设备,包括一些小型设备,例如小尺寸晶体管,SOTXXX Eutectic。为了消除模具裂纹缺陷,需要对整个装配过程进行优化;包括锯,芯片附着,引线键合,模具,电镀,修整/成型和最终测试。每个过程步骤都有其自身的风险,因此对所有可能的机会进行了全面分析。在晶圆锯切过程中,评估了几种锯切方法,包括单切,阶梯切,3通道切,切割方向以及各种刀片类型的选择。通过最佳的锯切工艺,可以将芯片切屑最小化到最低水平(仅几微米),从而将芯片开裂的风险降到最低。通过这种性能,进行了进一步的风险调查,以了解包装内的应力量。有2个重要的应力因素,芯片上的标志位置和对引线的修整/形状影响。为了最小化应力的影响,将管芯附着到应力最小的位置。至于装饰/形式,这涉及新设计的引线框架,并在生产中进行了试验。引线框架的设计优化是在符合合理的应力水平后完成的,该水平在微调/成型应力分析中计算得出。当对新的引线框架进行实际的修整/成型过程时,通过可靠性测试验证了实际性能。通过最佳的组装配置,进一步的安全措施取决于最终测试的能力。添加了2个其他测试参数,以提高筛选潜在的模具裂纹次品的效率。通过所有最佳装配和测试配置的总汇编,实际性能监控显示完全消除了模具裂纹的发生。该项目成为减少或消除模具裂纹项目的良好基准。

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