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Numerical analysis on MUF process for flip chip packaging

机译:倒装芯片MUF工艺的数值分析

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摘要

With merits like high I/O density, superior electrical and thermal performance, and small form factor, flip chip has become more and more widely used in electronic packages. Although the flip chip packaging process has been fairly improved, the conventional CUF (Capillary Underfill) process is a bottleneck that results in lower productivity and higher cost. MUF (Molded Underfill) process offers an alternative solution with advantages such as simplification of process, reduction of material cost and higher productivity. However, the extremely narrow gap between substrate and die makes it a big challenge to get optimal MUF material set and appropriate process conditions to cope with the serious void trapping issue. Besides, the process-induced w arpage is also a problem that affects yield and reliability. In this paper, the MUF process of a flip chip package has been studied using numerical analysis method. The cure-kinetic, rheological and chemical shrinkage properties of MUF compound were measured by DSC (Differential Scanning Calorimeter), DMA (Dynamic Mechanical Analyzer) and universal testing machine, respectively. A global model and a sectional model were developed for MUF injection analysis to simulate the melt front advancement and estimate possible mold void distribution. Warpage analysis considering both chemical shrinkage and CTE (Coefficient of Thermal Expansion) mismatch was performed afterwards. The MUF injection analysis showed mold void generated near the center of underfill area. The warpage analysis indicated that stresses caused by chemical shrinkage and CTE mismatch acted in opposite directions, and the overall warpage was dominated by CTE mismatch. Simulation results of injection analysis were validated by short shot experiment and SAM (Scanning Acoustic Microscopy) test, respectively, and the warpage prediction was verified by measurement data. Finally, MUF process setting with four parameters was optimized based on the established numerical mod- ls, three indicators of mold quality had been improved by 9.10%, 8.95% and 20.6% respectively.
机译:倒装芯片具有高I / O密度,卓越的电气和热性能以及小尺寸等优点,已越来越广泛地用于电子封装中。尽管倒装芯片封装工艺已得到相当大的改进,但常规的CUF(毛细管底部填充)工艺是导致生产率降低和成本提高的瓶颈。 MUF(模制底部填充)工艺提供了另一种解决方案,具有简化工艺,降低材料成本和提高生产率等优点。然而,基板和管芯之间的间隙非常窄,这对于获得最佳的MUF材料组和合适的工艺条件以应对严重的空隙捕获问题是一个巨大的挑战。此外,过程引起的扭曲也是影响产量和可靠性的问题。本文采用数值分析方法研究了倒装芯片封装的MUF工艺。分别通过DSC(差示扫描量热仪),DMA(动态力学分析仪)和通用测试机测量MUF化合物的固化动力学,流变和化学收缩性能。开发了用于MUF注射分析的全局模型和截面模型,以模拟熔体前沿发展并估计可能的模具空隙分布。随后进行了同时考虑化学收缩和CTE(热膨胀系数)不匹配的翘曲分析。 MUF注射分析表明在底部填充区域的中心附近产生了模具空洞。翘曲分析表明,由化学收缩和CTE失配引起的应力作用方向相反,整体翘曲主要由CTE失配主导。分别通过短期试验和SAM(扫描声显微镜)试验验证了注射分析的模拟结果,并通过测量数据验证了翘曲预测。最后,在建立的数值模型的基础上优化了具有四个参数的MUF工艺设置,三个模具质量指标分别提高了9.10%,8.95%和20.6%。

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