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Design and implementation of telescopic OTA in 8 bit second-order continuous-time band-pass Sigma-Delta ADC

机译:8位二阶连续时间带通Sigma-Delta ADC的伸缩OTA的设计与实现

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In this paper, a technique to design the 8 bit continuous-time band-pass Sigma-Delta converters for 70 MHz is presented. The conversion from discrete-time (z-domain) loop-filter transfer function into continuous-time (s-domain) is done by using Impulse-invariant-transformation. The transconductor-capacitor filter is used to implement continuous-time loop-filter. A latched-type comparator and a TSPC D Flip-flop are being used as the quantizer of the Sigma-Delta converter. The decimation filter is designed by a CIC Filter and an FIR filter for high-speed. A full adder cell and a TSPC D Flip-flop are used as basic building blocks of CIC Filter and FIR Filter. The 8 bit second-order continuous Sigma-Delta converter circuit has been implemented in Cadence using 180nm CMOS technology and the total power consumption is 34.48 mW. At a supply voltage of 3 V, the maximum SNR is measured to be 49.92 dB, ENOB is measured to be 8.29 bites, propagation delay is measured to be 2.56ns which corresponds to a resolution of 8 bits.
机译:本文提出了一种设计用于70 MHz的8位连续时间带通Sigma-Delta转换器的技术。从离散时间(z域)环路滤波器传递函数到连续时间(s域)的转换是通过使用脉冲不变变换完成的。跨导电容器滤波器用于实现连续时间环路滤波器。锁存型比较器和TSPC D触发器被用作Sigma-Delta转换器的量化器。抽取滤波器由用于高速的CIC滤波器和FIR滤波器设计。完整的加法器单元和TSPC D触发器用作CIC滤波器和FIR滤波器的基本构建块。 Cadence已使用180nm CMOS技术实现了8位二阶连续Sigma-Delta转换器电路,总功耗为34.48 mW。在3 V的电源电压下,最大SNR被测量为49.92 dB,ENOB被测量为8.29位,传播延迟被测量为2.56ns,对应于8位的分辨率。

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