Analysis of sampling clock jitter effect on the SNR of two RF sampling receivers

摘要

Today the RF sampling receivers have divided into direct sampling receivers with an ADC converter for low RF signals and direct pulse sampling receivers for high RF signals. Factors that affect the SNR of the two RF sampling systems are analyzed. Clock jitter is proved to be the key factor affecting RF sampling. This paper analyzes the cause of clock jitter and the relationship between jitter error and the input signal frequency, then gives the formula of SNR with jittered noise of the two receivers. Simulation results are given to verify the rational analysis. The results show that the SNR decreases with the increases of input signal frequency, and intensive jittered clock can also result in a serious deterioration of SNR.