The CAKE clocking and the trapezoidal clocking schemes: Principles and demo tests

摘要

A novel clock distribution technique, the Cable Automatic sKew Elimination (CAKE) clocking scheme has been developed and presented in this paper. In this scheme, clock pulses are driven into a cable and reflected from the high impedance receiving end. At the driving end, a cake-shaped waveform is seen and with 1/4 of the full pulse amplitude threshold, the output logic pulse width from a comparator carries cable delay information. Using a time-to-digital converter (TDC), the cable delay variation due to temperature change can be monitored and compensated for. The philosophy behind the CAKE clocking scheme is to keep the receiving end as simple as possible while implement extra circuitry in the transmitting end. Another clocking technique based on the same philosophy is the trapezoidal clocking scheme that we developed in our previous work. Demo tests of both the CAKE clocking and the trapezoidal clocking schemes are presented in this paper.