Design and development of high bit rate QPSK demodulator

摘要

The Quadrature Phase Shift Keying(QPSK) demodulator being presented here is designed based on Modified Costas loop technique to demodulate data rates upto 2 × 200Mbps. This paper highlights the design challenges involved in handling very high data rates in the analog domain with minimum cross-talk between I & Q chains and distortion in the demodulated signal. This paper also discusses about the ambiguity free lock detection in the Costas loop. Achieved Bit Error Rate(BER) performance with analog implementation has been quite encouraging.