首页> 外文会议>2013 IEEE 31st International Conference on Computer Design >Low-current probabilistic writes for power-efficient STT-RAM caches
【24h】

Low-current probabilistic writes for power-efficient STT-RAM caches

机译:低电流概率写入,用于省电的STT-RAM高速缓存

获取原文
获取原文并翻译 | 示例

摘要

MRAM has emerged as one of the most attractive non-volatile solutions due to fast read access, low leakage power, high bit density, and long endurance. However, the high power consumption of write operations remains a barrier to the commercial adoption of MRAM technology. This paper addresses this problem by introducing low-current probabilistic writes (LCPW), a technique that reduces write access energy by lowering the amplitude of the write current pulse. Although low current pulses no longer guarantee successful bit write operations, we propose and evaluate a simple technique to ensure correctness and achieve significant power reduction over a typical MRAM implementation.
机译:由于快速读取访问,低泄漏功率,高位密度和长寿命,MRAM已成为最有吸引力的非易失性解决方案之一。但是,写操作的高功耗仍然是MRAM技术商业应用的障碍。本文通过引入低电流概率写入(LCPW)解决了这一问题,该技术通过降低写入电流脉冲的幅度来降低写入访问能量。尽管低电流脉冲不再保证成功的位写入操作,但我们提出并评估了一种简单的技术,以确保正确性并在典型的MRAM实现上实现显着的功耗降低。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号