Digital Compensation for Timing Mismatches in Interleaved ADCs

摘要

This paper describes a digital method of reducing timing mismatch effects in time-interleaved ADCs used in ATE systems: we use cross-correlation among channel ADC outputs to detect channel timing skew, and make successive-approximation adjustments to our proposed linear-phase-digital delay filter to compensate for the timing skew. Simulation results validate the effectiveness of the proposed method. We found that using multitone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a singletone input signal. Since our proposed approach is fully digital, it is reliable, and suitable for fine CMOS implementation.