Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

摘要

For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for LG=20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked ID-VG's. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD=±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.